1. M. Almadhoun and H.N. Alshareef,  (12T&I0026-US-PSP), "High performance all-organic nanocomposites with giant dielectric permittivity, low dielectric loss, and low percolation threshold" filed at the US Patent Office on 09-10-2012 as Serial Number 61/711279 

2. U. Bhansal, M.A. Khan, and H.N. Alshareef, (12T&I0025-US-PSP), "Solution-processed flexible and transparent resistive WORM memory fabricated from a single polymer material i.e. Poly(3,4-ethylenedioxythiophene): poly(styrene sulfonic acid) [PEDOT:PSS]" was filed at the Patent Office on 09-10-2012 as Serial Number 61/711281.

3. M.A. Khan U. Bhansal, , and H.N. Alshareef (12T&I0018-US-PSP[2]), "FERROELECTRIC DEVICES, INTERCONNECTS, AND METHODS OF MANUFACTURE THEREOF " was filed at the Patent Office on 26-09-2012 as Serial Number 61/705782. 

4.Unnat Bhansali, M. Khan, and H.N. Alshareef, “Polymeric Global Interconnects for Flexible Electronics Applications”, filed June, 2012.

5.M.A. Khan and H.N. Alshareef, “Single Material Flexible Memory Device”, disclosed May 2012. Patent application in preparation. 

6.US patent no. 7906441, “System and method to mitigate oxide growth in a gate dielectric”, issued 2011.

7.US patent no. 7682988, “Thermal treatment of nitride oxide to improve negative bias thermal instability”, issued 2010. 

8.US patent no. 7514308, “CMOS device having different amounts of nitrogen in the nmos and pmos dielectric layer”, issued 2009. 

9.US patent no. 7582571, “Dual Metal Gates for 3-D field effect transistor (MUGFET)”, issued 2009. 

10.US patent no. 7345001, “Gate dielectric having flat nitrogen profile and method of manufacture therefore”, issued 2008. 

11.US patent no. 7402524, “Post high voltage gate oxide pattern, high vacuum surface outgas treatment”, issued 2008.

12.US patent no. 7227201, “CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers”.  Issued 2007. 

13.US patent no. 7226826, “Semiconductor device having multiple work functions and method of manufacture therefore”.  Issued 2007. 

14.US patent no. 7206215, “Antifuse having tantalum oxynitride film and method for making same”.  Issued 2007.

15.US patent no. 7176079, "Method of fabricating a semiconductor device with a wet oxidation with steam process".  Issued 2007.

16.US patent no. 7087440, “Monitoring of nitrided oxide gate dielectrics by determination of a wet etch rate”.  Issued 2007.

17.US patent no. 7064052, “Monitoring Method of processing a transistor gate dielectric film with steam”.  Issued 2006.

18.US patent no. 7049242, “Post high voltage gate dielectric pattern plasma surface treatment”.  Issued 2006. 

19.US patent no. 7038265, “Capacitor having tantalum oxynitride film and method for making same”.  Issued 2006. 

20.US patent no. 7022623, “Method of fabricating a semiconductor device with a dielectric film using a wet oxidation with steam process”.  Issued 2006. 

21.US patent no. 7018925, “Monitoring Post high voltage gate oxide pattern high-vacuum outgas surface treatment”.  Issued 2006.

22.US patent no. 6955996, “Method for stabilizing high pressure oxidation of a semiconductor device”.  Issued 2005. 

23.US patent no. 6949477, “Method of fabricating a capacitive element for a semiconductor device”.  Issued 2005. 

24.US patent no. 6943392, “Capacitors having a capacitor dielectric layer comprising a metal oxide having multiple different metals bonded with oxygen”.  Issued 2005. 

25.US patent no. 6924239, “Method for removal of hydrocarbon contamination on gate oxide prior to non-thermal nitridation using "spike" radical oxidation”.  Issued 2005. 

26.US patent no. 6921703, “System and method for mitigating oxide growth in a gate dielectric”.  Issued 2005. 

27.US patent no. 6872639, “Fabrication of semiconductor devices with transition metal boride films as diffusion barriers”.  Issued 2005.

28.US patent no. 6864527, “Capacitor having tantalum oxynitride film and method for making same”.  Issued 2005.

29.US patent no. 6773981, “Methods of forming capacitors”.  Issued 2004.

30.US patent no. 6737696, “DRAM capacitor formulation using a double-sided electrode”.  Issued 2004.

31.US patent no. 6730566, “Method for non-thermally nitrided gate formation for high voltage devices”.  Issued 2004. 

32.US patent no. 6720607, “Method for improving the resistance degradation of thin film capacitors”.  Issued 2004.

33.US patent no. 6673689, “Double layer electrode and barrier system on hemispherical grain silicon for use with high dielectric constant materials”.  Issued 2004. 

34.US patent no. 6635547, “DRAM capacitor formulation using a double-sided electrode”.  Issued 2003. 

35.US patent no. 6614082, “Fabrication of semiconductor devices with transition metal boride films as diffusion barriers”.  Issued 2003. 

36.US patent no. 6610211, “Method of processing internal surfaces of a chemical vapor deposition reactor”.  Issued 2003.

37.US patent no. 6596651, “Method for stabilizing high pressure oxidation of a semiconductor device”.  Issued 2003. 

38.US patent no. 6518121, “Boride electrodes and barriers for cell dielectrics”.  Issued 2003. 

39.US patent no. 6458645, “Capacitor having tantalum oxynitride film and method for making same”.  Issued 2002. 

40.US patent no. 6451661, “DRAM capacitor formulation using a double-sided electrode”.  Issued 2002. 

41.US patent no. 6423649, “Method and apparatus for stabilizing high pressure oxidation of a semiconductor device”.  Issued 2002.

42.US patent no. 6400552, “Capacitor with conductively doped Si-Ge alloy electrode”.  Issued 2002. 

43.US patent no. 6399459, “Double layer electrode and barrier system on hemispherical grain silicon for use with high dielectric constant materials and methods for fabricating the same”.  Issued 2002.

44.US patent no. 6351005, “Integrated capacitor incorporating high K dielectric”.  Issued 2002. 

45.US patent no. 6316800, “Boride electrodes and barriers for cell dielectrics”.  Issued 2001.

46.US patent no. 6291364, “Method and apparatus for stabilizing high pressure oxidation of a semiconductor device”.  Issued 2001. 

47.US patent no. 6281543, “Double layer electrode and barrier system on hemispherical grain silicon for use with high dielectric constant materials and methods for fabricating the same”.  Issued 2001.

48.US patent no. 6258655, “Method for improving the resistance degradation of thin film capacitors”.  Issued 2001. 

49.US patent no. 6255186, “Methods of forming integrated circuitry and capacitors having a capacitor electrode having a base and a pair of walls projecting upwardly therefrom”.  Issued 2001. 

50.US patent no. 6239459, “Capacitors, methods of forming capacitors and integrated circuitry”.  Issued 2001. 

51.US patent no. 6162744, “Method of forming capacitors having high-K oxygen containing capacitor dielectric layers, method of processing high-K oxygen containing dielectric layers, method of forming a DRAM cell having having high-K oxygen containing capacitor dielectric layers”.  Issued 2000. 

52.US patent no. 6124164, “Method of making integrated capacitor incorporating high K dielectric”.  Issued 2000. 

53.US patent no. 6096127, “Tunable dielectric films having low electrical losses”.  Issued 2000. 

54.US patent no. 6082375, “Method of processing internal surfaces of a chemical vapor deposition reactor”.  Issued 2000. 

55.US patent no. 5555486, “Hybrid metal/metal oxide electrodes for ferroelectric capacitors”.  Issued 2000.